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1. general description the pcf2119x is a low power cmos 1 lcd controller and driver, designed to drive a dot matrix lcd display of 2-lines by 16 characters or 1-line by 32 characters with 5 8 dot format. all necessary functions for the display are provided in a single chip, including on-chip generation of lcd bias voltages, resu lting in a minimum of external components and lower system current consumption. the pcf2119x interfaces to most microcontrollers via a 4-bit or 8-bit bus or via the 2-wire i 2 c-bus. the chip contains a character generator and displays alphanumeric and kana (japanese) characters. the letter ?x? in pcf2119x characterizes the bu ilt-in character set. various character sets can be manufactured on request. in addition 16 user defined symbols (5 8 dot format) are available. 2. features and benefits ? single-chip lcd controller and driver ? 2-line display of up to 16 characters plus 160 icons or 1-line display of up to 32 characters plus 160 icons ? 5 7 character format plus cursor; 5 8 for kana (japanese) and user defined symbols ? reduced current consumption while displaying icons only ? icon blink function ? on-chip: ? configurable 4, 3, or 2 times voltage multiplier generating lcd supply voltage, independent of v dd , programmable by instruction (external supply also possible) ? temperature compensation of on-chip generated v lcdout : ? 0.16 %/k to ? 0.24 %/k (programmable by instruction) ? generation of intermediate lcd bias voltages ? oscillator requires no external componen ts (external clock also possible) ? display data ram (ddram): 80 characters ? character generator rom (cgrom): 240 characters (5 8) ? character generator ram (cgram): 16 characters (5 8); 4 characters used to drive 160 icons, 8 characters used if icon blink feature is used in application ? 4-bit or 8-bit parallel bus and 2-wire i 2 c-bus interface ? manufactured in silicon gate cmos process ? 18 row and 80 column outputs ? multiplex rates 1:18 (2-line di splay or 1-line display), 1:9 (for 1-line display of up to 16 characters and 80 icons) and 1:2 (for icon only mode) pcf2119x lcd controllers/drivers rev. 9 ? 14 april 2011 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 20 .
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 2 of 83 nxp semiconductors pcf2119x lcd controllers/drivers ? uses common 11 code in struction set (extended) ? logic supply voltage: v dd1 ? v ss1 = 1.5 v to 5.5 v (chip may be driven with two battery cells) ? lcd supply voltage: v lcdout ? v ss2 = 2.2 v to 6.5 v ? v lcd generator supply voltage: v dd2 ? v ss2 = 2.2 v to 4 v and v dd3 ? v ss2 =2.2vto4v ? direct mode to save current consumption for icon mode and multiplex drive mode 1:9 (depending on v dd2 value and lcd liquid properties) ? very low current consumption (20 a to 200 a): ? icon mode: < 25 a ? power-down mode: < 2 a ? icon mode is used to save current. when only icons are displayed, a much lower lcd operating voltage can be used and the switching frequency of the lcd outputs is reduced; in most applications it is possible to use v dd as lcd supply voltage 3. applications ? telecom equipment ? portable instruments ? point-of-sale terminals 4. ordering information [1] with pi scratch protection coating, thickness 3.6 m. table 1. ordering information type number package name description version pcf2119au/2da/2 pcf2119x b are die: 168 bumps; 7.59 1.71 0.38 mm pcf2119x pcf2119du/2/2 pcf2119x bar e die: 168 bumps; 7.59 1.71 0.38 mm pcf2119x pcf2119fu/2/f2 pcf2119x bare die: 168 bumps; 7.59 1.71 0.38 mm pcf2119x pcf2119iu/2da/2 pcf2119x bare die: 168 bumps; 7.59 1.71 0.38 mm pcf2119x pcf2119ru/2/f2 pcf2119x ba re die: 168 bumps; 7.59 1.71 0.38 mm pcf2119x pcf2119ru/2db/2 [1] pcf2119x bare die: 168 bumps; 7.59 1.71 0.38 mm pcf2119x pcf2119su/2/f2 pcf2119x ba re die: 168 bumps; 7.59 1.71 0.38 mm pcf2119x
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 3 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 5. marking table 2. marking codes type number marking code pcf2119au/2da/2 pc2119-2 pcf2119du/2/2 pc2119-2 pcf2119fu/2/f2 pc2119-2 pcf2119iu/2da/2 pc2119-2 pcf2119ru/2/f2 pc2119-2 pcf2119ru/2db/2 pc2119-2 pcf2119su/2/f2 pc2119-2
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 4 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 6. block diagram fig 1. block diagram of pcf2119x mgw57 1 cursor and data control shift register 5 12 bit data latches column drivers 80 5 80 character generator ram (128 5) (cgram) 16 characters character generator rom (cgrom) 240 characters display data ram (ddram) 80 characters/bytes address counter (ac) instruction decoder instruction register row drivers shift register 18-bit bias voltage generator v lcd generator busy flag data register (dr) i/o buffer oscillator timing generator display address counter v dd1 v lcdout v ss1 t1 v lcdin 44 to 49 v lcdsense 36 37 to 43 22 to 29 20 t2 21 t3 153 163 1 to 6 v dd2 7 to 14 v dd3 15 to 18 c1 to c80 r17dup r1 to r18 osc pd pcf2119x db0 to db2 db3/sa0 db4 to db7 e r/w rs scl sda 18 18 80 5 168 100 155 por 154 7 7 7 8 7 7 8 8 8 160 to 162 60 to 99, 101 to 140 51 to 59, 141 to 149 164 to 167 156, 157 151, 152 159 158 19 v ss2 30 to 35
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 5 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 7. pinning information 7.1 pinning viewed from active side. for mechanical details, see figure 49 . fig 2. pinning diagram of pcf2119x (bare die) mgw572 100 75 74 60 50 125 126 142 149 150 c40 r17dup c41 c65 c66 c80 r17 r1 r8 dummy c16 c15 c1 r18 r9 r16 dummy pcf2119x 49 44 1 151 158 168 7 15 19 20 21 22 30 37 34 35 v lcdin t3 por pd sda r/w rs db0 db1 db2 db3/sa0 db4 db5 db6 db7 osc e t1 t2 v lcdsense v ss2 v lcdout v ss2 v ss1 v dd3 scl v dd2 v dd1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 6 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 7.2 pin description table 3. pin description symbol pin description v dd1 1 to 6 supply voltage 1 (logic) v dd2 7 to 14 [1] supply voltage 2 (for high voltage generator) v dd3 15 to 18 [1] supply voltage 3 (for high voltage generator) e19 [2] data bus clock input ? set high to signal the start of a read or write operation ? data is clocked in or out of the chip on the negative edge of the clock t1 and t2 20 and 21 test pins ? must be connected to v ss1 v ss1 22 to 29 [3] ground supply voltage 1 ? for all circuits, except of high voltage generator v ss2 30 to 35 [3] ground supply voltage 2 ? for high voltage generator v lcdsense 36 input for voltage multiplier regulation circuitry and for the bias level generation ? if v lcd is generated internally then this pin must be connected to v lcdout and v lcdin ? if v lcd is generated externally then this pin must be connected to v lcdin only v lcdout 37 to 43 v lcd output ? if v lcd is generated internally then this pin must be connected to v lcdin and to v lcdsense ? if v lcd is generated externally then this pin must be left open-circuit v lcdin 44 to 49 input for lcd bias level generator ? if v lcd is generated internally then this pin must be connected to v lcdout and to v lcdsense ? if v lcd is generated externally then this pin must be connected to v lcdsense and to the external v lcd power supply dummy 50 [4] - r8 to r1, r17, r17dup, r18, r9 to r16 51 to 58, 59, 100 141, 142 to 149 lcd row driver output ? r17 has two pins: r17 and r17dup ? r17 and r18 drive the icons c80 to c41, c40 to c1 60 to 99, 101 to 140 lcd column driver output dummy 150 [4] - scl 151 and 152 [5] i 2 c-bus serial clock input t3 153 test pin ? open-circuit ? not user accessible por 154 external power-on reset (por) input
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 7 of 83 nxp semiconductors pcf2119x lcd controllers/drivers [1] always put v dd2 =v dd3 . [2] when the i 2 c-bus is used, the parallel interface pin e must be low. [3] the substrate (rear side of the die) is wired to v ss but should not be electrically connected. [4] on the device connected to v ss1 . [5] when the parallel bus is used, the pins scl and sda must be connected to v ss1 or v dd1 ; they must not be left open-circuit. [6] in the i 2 c-bus read mode, ports db7 to db4 and db2 to db0 should be connected to v dd1 or left open-circuit. [7] when the 4-bit interface is used without reading out from the pcf2119x (bit r/w is set permanently to logic 0), the unused ports db4 to db0 can either be set to v ss1 or v dd1 instead of leaving them open-circuit. pd 155 power-down mode select ? for normal operation, pin pd must be low sda 156 and 157 [5] i 2 c-bus serial data input/output r/w 158 read/write input ? pin r/w = high selects the read operation ? pin r/w = low selects the write operation ? this pin has an internal pull-up resistor rs 159 register select pin ? this pin has an internal pull-up resistor db0 to db2, db3/sa0, db4 to db7 160 to 162, 163, 164 to 167 [6] [7] 8 bit bidirectional data bus (bit 0 to bit 7) ? the 8-bit bidirectional data bus (3-state) transfers data between the microcontroller and the pcf2119x ? pin db7 may be used as the busy flag, signalling that internal operations are not yet completed ? 4-bit operations the 4 higher order lines db7 to db4 are used, db3 to db0 must be left open-circuit ? data bus line db3 has an alternative function (sa0) as the i 2 c-bus address pin ? each data line has its own internal pull-up resistor osc 168 oscillator or external clock input ? when the on-chip oscillator is used this pin must be connected to v dd1 table 3. pin description ?continued symbol pin description
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 8 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 8. functional description 8.1 oscillator and timing generator the internal logic and the lcd drive signals of the pcf2119x are timed by the frequency f clk which equals either the built in oscillator frequency f osc or an external clock frequency f clk(ext) . 8.1.1 timing generator the timing generator produces the various sig nals required to drive the internal circuitry. internal chip operation is not disturbed by operations on the data buses. 8.1.2 internal clock to use the on-chip oscillator, pin osc must be connected to v dd1 . the on-chip oscillator provides the clock signal for the display system. no external components are required. 8.1.3 external clock if an external clock will be used, the input is at pin osc. the resulting display frame frequency is given by: (1) remark: only in the power-down mode the clock is allowed to be stopped (pin osc connected to v ss ), otherwise the lcd is frozen in a dc state, which is not suitable for the liquid crystals. 8.2 reset function and po wer-on reset (por) the pcf2119x must be reset externally when power is turned on. if no external reset is performed, the chip might start-up in an unwanted state. for the external reset, pin por has to be acti ve high. the reset has to be active for at least 3 oscillator periods in or der for the reset to be executed . if the internal oscillator is used, the minimum reset activity time follows from the lowest possibl e oscillator frequency (f osc = 140 khz, t osc ~71 s, 3 t osc ~215 s). the internal oscilla tor start-up time is 200 s (typ) up to 300 s (max) after power-on. in case that an external oscillator is used, t osc is dependent from f osc(ext) . afterwards the chip executes the clear_display instruction, which requires 165 oscillator cycles. after the reset the chip has the state shown in ta b l e 4 and is then ready for use. f fr f osc 3072 ----------- - =
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 9 of 83 nxp semiconductors pcf2119x lcd controllers/drivers [1] the busy flag (bf) indicates the busy state (bit bf = 1) until in itialization ends. the busy state lasts 2 ms. the chip may als o be initialized by software (see table 44 and table 45 ). 8.3 power-down mode the chip can be put into power-down mode by applying a high-level to pin pd. in power-down mode all stat ic currents are switched off (no in ternal oscillator, no bias level generation and all lcd outputs are internally connected to v ss ). during power-down, info rmation in the ram and the chip state are preserved. instruction execution during power-down is possible when pin osc is externally clocked. table 4. state after reset step function control bit and register state description reference 1 clear_display - - ta b l e 1 6 2 entry_mode_set bit i_d = 1 incremental cursor move direction ta b l e 1 8 bit s = 0 no display shift 3 display_ctl bit d = 0 display off ta b l e 1 9 bit c = 0 cursor off bit b = 0 cursor character blink off 4 function_set bit dl = 1 8-bit interface ta b l e 1 2 bit m = 0 1-line display bit sl = 0 1:18 multiplex drive mode bit h = 0 normal instruction set 5 default address pointer to ddram [1] -- ta b l e 2 2 6 icon_ctl bit im = 0 character mode, full display ta b l e 2 5 bit ib = 0 icon blink disabled 7 screen_conf bit l = 0 default configuration ta b l e 2 3 disp_conf bit p = 0; bitq=0 default configurations ta b l e 2 4 8 temp_ctl bit tc1 = 0; bit tc2 = 0 default temperature coefficient ta b l e 2 8 9 vlcd_set register v a =0; register v b =0 v lcd generator off ta b l e 3 2 10 i 2 c-bus interface reset - - - 11 hv_gen bit s1 = 1; bit s0 = 0 v lcd generator set to 3 internal stages (4 voltage multipliers) ta b l e 3 0
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 10 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 8.4 lcd supply voltage generator the lcd supply voltage may be generated on-chip. the v lcd generator is controlled by two internal 6-bit registers: v a and v b . register v a is programmed with the voltage for character mode and register v b with the voltage for icon mode. the nominal lcd operating voltage at room temperature is given by equation 2 : (2) where v x is the integer value of the register v a or v b . it should be noted that v lcd is sometimes referred as the lcd operating voltage (v oper ). 8.4.1 programming ranges possible values for v a and v b are between 0 to 63. v lcd nom () v x 0.08 1.82 + = table 5. values of v a and v b and the corresponding v lcd values all values at t ref =27 c; allowed values are highlighted. integer values of v a and v b corresponding value of v lcd in v integer values of v a and v b corresponding value of v lcd in v integer values of v a and v b corresponding value of v lcd in v 0 v lcd switched off 22 3.58 44 5.34 11.90 23 3.66 45 5.42 21.98 24 3.74 46 5.50 32.06 25 3.82 47 5.58 42.14 26 3.90 48 5.66 52.22273.98495.74 62.30284.06505.82 72.38294.14515.90 82.46304.22525.98 92.54314.30536.06 10 2.62 32 4.38 54 6.14 11 2.70 33 4.46 55 6.22 12 2.78 34 4.54 56 6.30 13 2.86 35 4.62 57 6.38 14 2.94 36 4.70 58 6.46 15 3.02 37 4.78 59 6.54 16 3.10 38 4.86 60 6.62 17 3.18 39 4.94 61 6.70 18 3.26 40 5.02 62 6.78 19 3.34 41 5.10 63 6.86 20 3.42 42 5.18 21 3.50 43 5.26
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 11 of 83 nxp semiconductors pcf2119x lcd controllers/drivers remarks: ? values producing more than 6.5 v at operating temperature are not allowed. operation above this voltage may dama ge the device. when programming the operating voltage, the temperature coefficient of v lcdout must be taken into account. ? values below 2.2 v are below the specified operating range of the chip and are therefore not allowed. when the lcd supply voltage is generated on-chip, the v lcd pins should be decoupled to v ss with a suitable capacitor. the generated v lcdout is independent of v dd and is temperature compensated. in equation 2 the internal charge pump is not considered. however, if the supplied voltage to v dd2 and v dd3 is below the required v lcd it is necessary to use the internal charge pump. the multiplication factor has to be set such, that v dd2 and v dd3 (which are equal) multiplied with the pr ogrammed multiplication factor exceeds the required v lcd under all circumstances (i.e. at low temperatures and along with the temperature compensation - see section 10.2.3.4 ). if still a higher multiplication factor is chosen, v lcd will not increase (it is set by equation 2 ) but the current that can be deliv ered will be higher . also current consumption increases (see section 16.6 ). when the v lcd generator and the direct mode are switched off, an external voltage may be supplied at connected pins v lcdin and v lcdout . v lcdin and v lcdout may be higher or lower than v dd2 . in direct mode (see icon_ctl instruction, section 10.2.3.3 ) the internal v lcd generator is turned off and the v lcdout output voltage is directly connected to v dd2 . this reduces the current consumption depending on v dd2 value and lcd liquid properties. the v lcd generator ensures that, as long as v dd2 and v dd3 are in the valid range (2.2 v to 4 v), the required peak voltage v lcd = 6.5 v can be generated at any time. 8.5 lcd bias voltage generator the intermediate bias voltages for the lcd display are also generated on-chip. this removes the need for an external resistive bi as chain and significantly reduces the system current consumption. the optimum value of v lcd depends on the multiplex rate, the lcd threshold voltage (v th ) and the number of bias levels. using a 5-level bias scheme for the 1:18 multiplex rate allows v lcd < 5 v for most lcd liquids. the intermediate bias levels for the different multiplex rates are shown in ta b l e 6 . these bias levels are automatically set to the given values when switching to the corresponding multiplex rate.
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 12 of 83 nxp semiconductors pcf2119x lcd controllers/drivers the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 3 and the rms off-state voltage (v off(rms) ) with equation 4 : (3) (4) where the values of a are a=2 for 1 ? 4 bias a=3 for 1 ? 5 bias and the values for n are n = 2 for 1:2 multiplex rate n = 9 for 1:9 multiples rate n = 18 for 1:18 mu ltiplex rate. discrimination (d) is the ratio of v on(rms) to v off(rms) and is determined from equation 5 (5) 8.5.1 electro-optical performance suitable values for v on(rms) and v off(rms) are dependant on the lcd liquid used. the rms voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. for any given liquid, there are two threshold values defined. one point is at 10 % relative transmission (at v low ) and the other at 90 % relative transmission (at v high ), see figure 3 . for a good contrast performance, the following rules should be followed: (6) (7) table 6. bias levels as a function of multiplex rate multiplex rate number of bias levels bias voltages v 1 v 2 v 3 v 4 v 5 v 6 1:18 5 v lcd v ss 1:9 5 v lcd v ss 1:2 4 v lcd v ss 3 4 -- - v lcd v ss ? () 1 2 -- - v lcd v ss ? () 1 2 -- - v lcd v ss ? () 1 4 -- - v lcd v ss ? () 3 4 -- - v lcd v ss ? () 1 2 -- - v lcd v ss ? () 1 2 -- - v lcd v ss ? () 1 4 -- - v lcd v ss ? () 2 3 -- - v lcd v ss ? () 2 3 -- - v lcd v ss ? () 1 3 -- - v lcd v ss ? () 1 3 -- - v lcd v ss ? () v on rms () a 2 2a n ++ n 1a + () 2 ----------------------------- - v lcd = v off rms () a 2 2a ? n + n 1a + () 2 ----------------------------- - v lcd = d v on rms () v off rms () ---------------------- - a1 + () 2 n 1 ? () + a1 ? () 2 n 1 ? () + ------------------------------------------- - == v on rms () v high v off rms () v low
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 13 of 83 nxp semiconductors pcf2119x lcd controllers/drivers v on(rms) and v off(rms) are properties of the display driver and are affected by the selection of a, n (see equation 3 to equation 5 ) and the v lcd voltage. v low and v high are properties of the lcd liquid and can be provided by the module manufacturer. it is important to match the module properties to those of the driver in order to achieve optimum performance. 8.6 lcd row and column drivers the pcf2119x contains 18 row and 80 column drivers, which drive the appropriate lcd bias voltages in sequence to the display in accordance with the data to be displayed. r17 and r18 drive the icon rows. unused outputs should be left open. the bias voltages and the timing are selected automatically when the number of lines in the display is selected. figure 4 to figure 6 show typical waveforms. fig 3. electro-optical characteristic: relative transmission curve of the liquid v rms [v] 100 % 90 % 10 % off segment grey segment on segment v low v high relative transmission 001aam35 8
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 14 of 83 nxp semiconductors pcf2119x lcd controllers/drivers state(n) marks intersection(row(x),col(n)) of pixel(x,n) v state(n) (t) = v col(n) (t) ? v row(x) (t). v state1 (t) = v col1 (t) ? v row1 (t). v state2 (t) = v col2 (t) ? v row1 (t). fig 4. waveforms for the 1:18 multiplex drive mode with 5 bias levels; character mode c1 frame n frame n +1 state 1 (on) state 2 (off) c2 c3 c4 c5 r18 r17 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 row 17 row 18 row 1 row 9 row 2 row 10 col 1 col 2 v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v lcd ? v lcd ? v lcd 0.5v lcd 0 0.25v lcd ? 0.25v lcd ? 0.5v lcd 0.5v lcd 0 0.25v lcd ? 0.25v lcd ? 0.5v lcd 12 3 18 state 2 state 1 12 3 18 013aaa140
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 15 of 83 nxp semiconductors pcf2119x lcd controllers/drivers state(n) marks intersection(row(x),col(n)) of pixel(x,n) v state(n) (t) = v col(n) (t) ? v row(x) (t). v state1 (t) = v col1 (t) ? v row1 (t). v state2 (t) = v col2 (t) ? v row1 (t). fig 5. waveforms for the 1:9 multiplex drive mode with 5 bias levels; character mode, r9 to r16 and r18 open c1 state 1 (off) state 2 (on) c2 c3 c4 c5 r17 r8 r7 r6 r5 r4 r3 r2 r1 013aaa141 12 3 9 123 9 frame n frame n +1 row 17 v lcd v 2 v 3 /v 4 v 5 v ss row 1 row 2 row 3 row 4 col 1 col 2 v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v 2 v 3 /v 4 v 5 v ss v lcd v lcd ? v lcd ? v lcd 0.5v lcd 0 0.25v lcd ? 0.25v lcd ? 0.5v lcd 0.5v lcd 0 0.25v lcd ? 0.25v lcd ? 0.5v lcd state 2 state 1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 16 of 83 nxp semiconductors pcf2119x lcd controllers/drivers state(n) marks intersection(row(x),col(n)) of pixel(x,n) v state(n) (t) = v col(n) (t) ? v row(x) (t). v state1 (t) = v col1 (t) ? v row17 (t). v state2 (t) = v col2 (t) ? v row17 (t). v state3 (t) = v col3 (t) ? v row1 to 16 (t). fig 6. waveforms for the 1:2 multiplex drive mode with 4 bias levels; icon mode only icons are driven (mux 1: 2) 013aaa14 2 state 1 (on) state 2 (off) state 3 (off) col 1 col 2 frame n frame n +1 row 17 row 18 row 1 to 16 col 1 on/off col 2 on/off col 3 on/off col 4 on/off v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd ? v lcd 0.66v lcd 0 0.33v lcd ? 0.33v lcd ? 0.66v lcd v lcd ? v lcd 0.66v lcd 0 0.33v lcd ? 0.33v lcd ? 0.66v lcd v lcd ? v lcd 0.66v lcd 0 0.33v lcd ? 0.33v lcd ? 0.66v lcd state 1 state 2 state 3
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 17 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 9. display data ram and rom 9.1 ddram the display data ram (ddram) stores up to 80 characters of display data represented by 8-bit character codes. ram locations whic h are not used for storing display data can be used as general purpose ram. the basic ram to display addressing scheme is shown in figure 7 , figure 8 and figure 9 . with no display shift the characters represente d by the codes in the first 32 ram locations starting at address 00h are displayed in line 1. all addresses are shown in hex. fig 7. ddram to display mapping: no shift all addresses are shown in hex. fig 8. ddram to display mapping: right shift 00 01 02 03 04 1d 1e 1f 20 21 4c 4d 4e 4f non-displayed ddram addresses 64 65 66 67 40 41 42 43 44 4d 4e 4f 50 51 00 01 02 03 04 0d 0e 0f 10 11 24 25 26 27 non-displayed ddram address line 1 line 2 mgk89 2 ddram address 2-line display/mux 1 : 9 mode 12345 303132 12345 141516 12345 141516 display position ddram address 1-line display mgl53 6 27 00 01 02 03 67 40 41 42 43 0c 0d 0e 4c 4d 4e ddram address line 1 line 2 2-line display/mux 1 : 9 mode 1 2 3 4 5 14 15 16 1 2 3 4 5 14 15 16
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 18 of 83 nxp semiconductors pcf2119x lcd controllers/drivers when data is written to or read from the ddram, wrap-around occurs from the end of one line to the start of the next line. when the display is shifted each line wraps around within itself, independently of the others. thus all lines are shifted and wrapped around together. the address ranges and wrap-around operati ons for the various modes are shown in ta b l e 7 . 9.2 cgrom the character generator rom (cgrom) contains 240 character patterns in a 5 8dot format from 8-bit character codes. figure 10 to figure 15 show the character sets that are currently implemented. all addresses are shown in hex. fig 9. ddram to display mapping: left shift table 7. address space and wrap-around operation mode 1 32 2 16 1 16 address space 00h to 4fh 00h to 27h; 40hto67h 00h to 27h read/write wrap-around (moves to next line) 4fhto00h 27hto40h; 67hto00h 27h to 00h display shift wrap-around (stays within line) 4fhto00h 27hto00h; 67hto40h 27h to 00h 01 04 05 41 42 43 44 45 0e 0f 10 4e 4f 50 ddram address line 1 line 2 2-line display/mux 1 : 9 mode 1 2 3 4 5 30 31 32 1 2 3 4 5 14 15 16 1 2 3 4 5 14 15 16 01 04 05 02 03 02 03 1e 1f 20 display position ddram address 1-line display mgk89 4
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 19 of 83 nxp semiconductors pcf2119x lcd controllers/drivers the first column (0000) is the cgram, the other 15 columns (0001 to 1111) are the cgrom. fig 10. character set ?a? in cgrom mce190 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 20 of 83 nxp semiconductors pcf2119x lcd controllers/drivers the first column (0000) is the cgram, the other 15 columns (0001 to 1111) are the cgrom. fig 11. character set ?d? in cgrom mce173 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 21 of 83 nxp semiconductors pcf2119x lcd controllers/drivers the first column (0000) is the cgram, the other 15 columns (0001 to 1111) are the cgrom. fig 12. character set ?f? in cgrom mgu552 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 22 of 83 nxp semiconductors pcf2119x lcd controllers/drivers the first column (0000) is the cgram, the other 15 columns (0001 to 1111) are the cgrom. fig 13. character set ?i? in cgrom 001aan760 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 23 of 83 nxp semiconductors pcf2119x lcd controllers/drivers the first column (0000) is the cgram, the other 15 columns (0001 to 1111) are the cgrom. fig 14. character set ?r? in cgrom mgl53 5 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 24 of 83 nxp semiconductors pcf2119x lcd controllers/drivers the first column (0000) is the cgram, the other 15 columns (0001 to 1111) are the cgrom. fig 15. character set ?s? in cgrom mgl534 xxxx 1111 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 25 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 9.3 cgram up to 16 user defined characters may be stored in the character generator ram (cgram). some cgram characters (see figure 22 ) are also used to drive icons: ? 6 cgram characters if icons blink and both icon rows are used in the application ? 3 cgram characters if no icons blink but bo th icon rows are used in the application ? 0 cgram characters if no icons are driven by the icon rows when the icons blink option is enabled, double the number of cgram characters are used since both the on and of f state of an icon is defined. the cgrom and cgram use a common address space, of which the first column is reserved for the cgram (see figure 10 to figure 15 ). figure 16 shows the addressing principle for the cgram. (1) character code bit 0 to bit 3 corr espond to cgram address bit 3 to bit 6. (2) cgram address bit 0 to bit 2 designate the character pattern line position. the 8th line is the cursor position and display is performed by logical or with the cursor. data in the 8th line will appear in the cursor position. lines are numbered from 0 to 7. (3) character pattern column positions correspond to cgram data bit 0 to bit 4, as shown in figure 10 to figure 15 . (4) as shown in figure 10 to figure 15 , cgram character patterns are selected when c haracter code bit 4 to bit 7 are all logic 0. cgram data = logic 1 corresponds to selection for display. (5) only bit 0 to bit 5 of the cgram address are set by t he set_cgram command. bit 6 can be set using the set_ddram command in the valid address range or by using the auto-increment feature during cgram write. all bits from bit 0 to bit 6 can be read using the bf_ac instruction. fig 16. relationship between cgram addresses, data and display patterns coa072 76543210 6543210 43210 higher order bits lower order bits lower order bits higher order bits lower order bits higher order bits 00000000 0000000 0 001 000 010 000 011 0 100 0 00 101 00 0 110 000 111 00000 000 000 001 0 0 0 010 00 00 011 100 101 00 00 110 00 00 111 00000 001 00000001 0001 00000010 00001111 00001111 00001111 00001111 01 00000 100 101 110 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111 character codes (ddram data) cgram address character patterns (cgram data) 43210 0 000 111 000 0 00 10 00 0 1 000 1 1 1 00 1 1 1 111 1 1 1 1 000 1 101 000 111 0 11 11 01 0 0 010 0 1 0 00 0 1 1 010 0 1 0 0 000 character code (cgram data) character pattern example 1 cursor position character pattern example 2 (4) (1) (1) (5) (2) (3)
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 26 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 9.4 cursor control circuit the cursor control circuit generates the cursor underline and/or cursor blink as shown in figure 17 at the ddram address contained in the address counter. fig 17. cursor and blink display examples fig 18. example of displays with icons 013aaa13 9 cursor 5 7 dot character font cursor display example alternating display blink display example cursor row 17 row 8 row 1 row 2 row 17 row 18 row 8 row 1 row 2 icon 1 icon 5 013aaa15 6
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 27 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 10. registers the pcf2119x has two 8-bit registers, an inst ruction register and a data register. only these two registers can be directly controlled by the microcontroller. before an internal operation, the control information is stored temporarily in these registers, to allow interfacing to various types of microcontrolle rs which operate at different speeds or to allow interface to peripheral control ics. the instruction set for the pa rallel interface is shown in ta b l e 11 together with their execution time. details about the parallel interface can be found in section 11.1 . examples of operations on a 4-bit bus are given in ta b l e 3 9 , on a 8-bit bus in ta b l e 4 0 , ta b l e 4 1 and table 42 . when using the i 2 c-bus, the instruction has to be commenced with a control byte as shown in ta b l e 8 . details about the i 2 c-bus interface can be found in section 11.2 . an example of operations on the i 2 c-bus is given in ta b l e 4 3 . [1] r/w is set together with the slave address (see ta b l e 3 3 ). instructions are of 4 types, those that: 1. designate pcf2119x functions like display format, data length, etc. 2. set internal ram addresses 3. perform data transfer with internal ram 4. others, like read ?busy flag? and read ?address counter? in normal use, type 3 instructions are used most frequently. however, automatic incrementing by 1 (or decrementing by 1) of in ternal ram addresses after each data write lessens the microcontroller program load. the dis play shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. during internal opera tion, no instructions other than the bf_ac instruction will be executed. because the busy flag is set to logic 1 while an instruction is being executed, check to ensure it is logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in ta b l e 11 . an instruction sent while the busy flag is logic 1 will not be executed. table 8. instruction set for i 2 c-bus commands control byte command byte i 2 c-bus command cors 000000db7db6db5db4db3db2db1db0 [1] table 9. control byte bit description bit symbol value description 7 co 0 last co ntrol byte 1 another control byte follows after data/command 6 rs 0 instruction register selected 1 data register selected 5 to 0 - 0 default logic 0
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 28 of 83 nxp semiconductors pcf2119x lcd controllers/drivers the rs bit determines which regi ster will be accessed and the r/w bit indicates if it is a read or a write operation (see ta b l e 1 0 ). [1] there is only write access to the instruction regist er, but read access to the busy flag (bf) and the address counter (ac) of the bf_ac instruction (see section 10.2.1.2 ). [2] write and read access. details of the instructions are ex plained in subsequent sections. 10.1 data register the data register temporarily stores data to be read fr om the ddram and cgram. prior to being read by the read_data instruction, data from the ddram or cgram, corresponding to the address in the instruction register, is written to the data register. 10.2 instruction register the instruction register stores instruction co des such as clear_display, curs_disp_shift, and address information for the display data ram (ddram) and character generator ram (cgram). the instruction register can be written to but not read from by the system controller. the instruction register is sectioned into basic, standard and extended instructions. bit h = 1 of the function_s et instruction (see section 10.2.1.1 ) sets the chip into extended instruction set mode. table 10. register access selection symbol value description rs register select 0 instruction register [1] 1 data register [2] r/w read/write 0 write operation 1 read operation
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 29 of 83 nxp semiconductors pcf2119x lcd controllers/drivers [1] the bits 0 to 7 correspond with the data bus lines db0 to db7. [2] f osc cycles. [3] no operation. [4] do not use. table 11. instruction register overview instruction bits [1] required clock cycles [2] reference rs r/w 7 6 5 4 3 2 1 0 basic instructions (bit h = 0 or 1) nop [3] 00000000003 - function_set 00001dl0mslh3 section 10.2.1.1 bf_ac 01bfac 0 section 10.2.1.2 read_data 1 1 read_data 3 section 10.2.1.3 write_data 1 0 write_data 3 section 10.2.1.4 standard instructions (bit h = 0) clear_display 0000000001165 section 10.2.2.1 return_home 00000000103 section 10.2.2.2 entry_mode_set00000001i_ds3 section 10.2.2.3 display_ctl 0000001dcb3 section 10.2.2.4 curs_disp_shift 000001scrl003 section 10.2.2.5 set_cgram 0 0 0 1 acg 3 section 10.2.2.6 set_ddram 0 0 1 add 3 section 10.2.2.7 extended instructions (bit h = 1) reserved [4] 0000000001- - screen_conf 000000001l3 section 10.2.3.1 disp_conf 00000001pq3 section 10.2.3.2 icon_ctl 0000001imibdm3 section 10.2.3.3 temp_ctl 00000100tc1tc23 section 10.2.3.4 hv_gen 0 0 0 10000s1s03 section 10.2.3.5 vlcd_set 0 0 1 v va or vb 3 section 10.2.3.6
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 30 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 10.2.1 basic instructions (bit h = 0 or 1) 10.2.1.1 function_set [1] when 4-bit width is selected, data is transmitted in tw o cycles using the parallel-bus. in a 4-bit application ports db3 to db0 should be left open-circuit (internal pull-ups). [2] default value after power-on in i 2 c-bus mode. [3] no impact if sl = 1. [4] due to the internal pull-ups on db3 to db0 in a 4-bi t application, the first function_set after power-on sets bits m, sl and h to logic 1. a second function_set mu st be sent to set bits m, sl and h to the required values. [5] independent of bit m and bit l of the screen_conf instruction (see section 10.2.3.1 ). only row 1 to row 8 and row 17 are used. all other rows must be left o pen-circuit. the ddram map is the same as in the 2 16 character display mode, however, t he second line cannot be displayed. 10.2.1.2 bf_ac instructions [1] it is recommended that the bf status is checked before the next write operation is started. table 12. function_set bit description bit symbol value description rs - 0 see ta b l e 1 0 r/w -0 7 to 5 - 001 fixed value 4dl interface data length (for parallel mode only) 0 [1] 2 4 bits (db7 to db4) 1 [2] 8 bits (db7 to db0) 3 - 0 unused 2m [3] number of display lines 0 1 line 32 characters 1 [4] 2 line 16 characters 1sl multiplex mode 0 1:18 multiplex drive mode, 1 32 or 2 16 character display 1 [4] [5] 1:9 multiplex drive mode, 1 16 character display 0h instruction set control 0 basic instruction set plus standard instruction set 1 [4] basic instruction set plus extended instruction set table 13. bf_ac bit bit symbol value description rs - 0 see ta b l e 1 0 r/w -1 7bf [1] read busy flag 0 next instruction will be executed 1 internal operation is in progress; next instruction will not be executed until bf = 0 6 to 0 ac 0000000 to 1111111 read address counter
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 31 of 83 nxp semiconductors pcf2119x lcd controllers/drivers busy flag: the busy flag indicates the internal status of the pcf2119x. a logic 1 indicates that the chip is busy and furt her instructions will not be acce pted. the busy flag is output to pin db7 when bit rs = 0 and bit r/w = 1. instructions should only be started after checking that the busy flag is at logic 0 or after waiting for the required number of cycles. address counter: the address counter is used by both cgram and ddram, and its value is determined by the previous set_ cgram and set_ddram instruction. after a read/write operation the address counter is automatically incremented or decremented by 1. the address counter value is output to the bus (db6 to db0) when bit rs = 0 and bit r/w =1. 10.2.1.3 read_data read_data from cgram or ddram: read_data reads binary 8-bit data from the cgram or ddram. the most recent ?s et address? command (set_cgram or set_ddram) determines w hether the cgram or ddram is to be read. the read_data instruction gates the content of the data register to the bus while pin e is high. after pin e goes low again, internal operation increments (or decrements) the address counter and stores ram data correspo nding to the new address counter into the data register. there are only three instructions that update the data register: ? set_cgram ? set_ddram ? read_data from cgram or ddram other instructions (e.g. write_data, curs_disp_shift, clear_display and return_home) do not modify the value of the data register. 10.2.1.4 write_data write_data to cgram or ddram: write_data writes binary 8-bit data to the cgram or the ddram. table 14. read_data bit description bit symbol value description rs - 1 see ta b l e 1 0 r/w -1 7 to 0 read_data 00000000 to 11111111 read data from cgram or ddram table 15. write_data bit description bit symbol value description rs - 1 see ta b l e 1 0 r/w -0 7 to 0 write_data 00000000 to 11111111 write data to cgram or ddram
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 32 of 83 nxp semiconductors pcf2119x lcd controllers/drivers the previous set_cgram or set_ddram comm and determines if data is written into cgram or ddram. after writin g, the address co unter automatically increments or decrements by 1, in accordance with the entry_mode_set (see section 10.2.2.3 ). only bit 4 to bit 0 of cgram data are valid, bit 7 to bit 5 are ?don?t care?. 10.2.2 standard instructions (bit h = 0) 10.2.2.1 clear_display clear_display: writes usually the character code 20h (blank pattern) into all ddram addresses except for the character set ?r? where the character code 20h is not a blank pattern. when using character set ?r?, the following alternative inst ruction set has to be used: 1. switch display off (display_ctl, bit d = 0). 2. write a blank pattern into all ddram addresses (write_data). 3. switch display on (display_ctl, bit d = 1). in addition clear_display ? sets the ddram address counter to logic 0 ? returns the display to its original position, if it was shifted. thus, the display disappears and the cursor or blink position goes to the left edge of the display ? sets entry mode bit i_d = 1 (increment mode); bit s of entry mode does not change the instruction clear_display requires extra execution time. this may be allowed by checking the busy flag bit bf or by waitin g until the 165 clock cycles have elapsed. the latter must be applied where no read-back options are foreseen, as in some chip-on-glass (cog) applications. 10.2.2.2 return_home return_home: sets the ddram address counter to logic 0 and switches a shifted display back to an unshifted state. the ddra m content remain unchanged. the cursor or blink position goes to the left of the fi rst display line. bit i_d and bit s of the entry_mode_set instruction remain unchanged. table 16. clear_display bit description bit symbol value description rs - 0 see ta b l e 1 0 r/w -0 7 to 0 - 00000001 fixed value table 17. return_home bit description bit symbol value description rs - 0 see ta b l e 1 0 r/w -0 7 to 0 - 00000010 fixed value
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 33 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 10.2.2.3 entry_mode_set bit i_d: when bit i_d = 1 the ddram or cgram address increments by 1 when data is written into or read from the ddram or cgram. the cursor or blink position moves to the right. when bit i_d = 0 the ddram or cgram address decrements by 1 when data is written into or read from the ddram or cgram. the cursor or blink position moves to the left. the cursor underline and cursor character blink are inhibited when the cgram is accessed. bit s: when bit s = 0, the display does not shift. during ddram write, when bit s = 1 and bit i_d = 0, the entire display shifts to the right; when bit s = 1 and bit i_d = 1, the entire display shifts to the left. thus it appears as if the cursor stands still and the display moves. the display does not shift when reading from the ddram, or when writing to or reading from the cgram. 10.2.2.4 display_ctl instructions table 18. entry_mode_set bit description bit symbol value description rs - 0 see ta b l e 1 0 r/w -0 7 to 2 - 000001 fixed value 1i_d address increment or decrement 0 ddram or cgram address decrements by 1, cursor moves to the left 1 ddram or cgram address increments by 1, cursor moves to the right 0s shift display to the left or right 0 display does not shift 1display shifts table 19. display_ctl bit description bit symbol value description rs - 0 see ta b l e 1 0 r/w -0 7 to 3 - 00001 fixed value 2d display on or off 0 display is off; chip is in power-down mode 1 display is on 1c cursor on or off 0 cursor is off 1 cursor is on 0b character blink on or off 0 character blink is off 1 character blink is on
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 34 of 83 nxp semiconductors pcf2119x lcd controllers/drivers bit d: the display is on when bit d = 1 and off when bit d = 0. display data in the ddram is not affected and can be displayed immediately by setting bit d = 1. when the display is off (bit d = 0) the chip is in partial power-down mode: ? the lcd outputs are connected to v ss ? the v lcd generator and bias generator are turned off three oscillator cycles are required after sending the ?display of f? instruction to ensure all outputs are at v ss , afterwards the oscillator can be st opped. if the oscillator is running during partial power-down mode (?display off? ) the chip can still execute instructions. even lower current consumption is obtained by inhibiting the oscillator (pin osc to v ss ). to e n s u r e i dd <1 a: ? the parallel bus ports db7 to db0 should be connected to v dd ? pins rs and r/w should be connected to v dd or left open-circuit ? pin pd should be connected to v dd recovery from power-down mode: ? pin pd should be connected back to v ss ? if necessary pin osc should be connected back to v dd ? a display_ctl instruction wit h bit d = 1 should be sent bit c: the cursor is displayed when bit c = 1 and inhibited when bit c = 0. even if the cursor disappears, bit i_d and bit s (see section 10.2.2.3 ) remain in operation during display data write. the cursor is displayed using 5 dots in the 8th line (see figure 17 ). bit b: the character indicated by the cursor blinks when bit b = 1. the character blink is displayed by switching between display characters and all dots on with a period of approximately 1 second, with 10.2.2.5 curs_disp_shift f blink f osc 52224 -------------- - = table 20. curs_disp_shift bit description bit symbol value description rs - 0 see table 10 r/w -0 7 to 4 - 0001 fixed value 3sc cursor move or display shift 0 move cursor 1 shift display 2rl shift or move to the right or left 0 left shift or move 1 right shift or move 1 to 0 - 00 fixed value
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 35 of 83 nxp semiconductors pcf2119x lcd controllers/drivers bits sc and rl: curs_disp_shift moves the cursor position or the display to the right or left without writing or reading display data. this function is used to correct a character or move the cursor through the display. in 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. when the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. the address counter content does not change if the only action performed is shift display (sc = 1) but increments or decrements with the shift cursor (sc = 0). 10.2.2.6 set_cgram set_cgram: sets the cgram address bits acg[5:0] into the address counter. data can then be written to or read from the cgram. remark: the cgram address uses the same addr ess register as the ddram address. this register consists of 7 bits. but with the set_cgram command, only bit 5 to bit 0 are set. bit 6 can be set using the set_ddram command first, or by using the auto-increment feature during cgram write. all bits 6 to 0 can be read using the bf_ac instruction. when writing to the lower part of the cgram, ensure that bit 6 of the address is not set (e.g. by an earlier ddram write). 10.2.2.7 set_ddram set_ddram: sets the ddram address bits add[6:0] into the address counter. data can then be written to or read from the ddram. table 21. set_cgram bit description bit symbol value description rs - 0 see table 10 r/w -0 7 to 6 - 01 fixed value 5 to 0 acg 000000 to 111111 set cgram address table 22. set_ddram bit description bit symbol value description rs - 0 see table 10 r/w -0 7 - 1 fixed value 6 to 0 add 0000000 to 1111111 set ddram address
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 36 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 10.2.3 extended instructions (bit h = 1) 10.2.3.1 screen_conf screen_conf: ? if bit l = 0, then the two halves of a split screen are connected in a standard way i.e. column 1/81, 2/82 to 80/160. ? if bit l = 1, then the two halves of a split sc reen are connected in a mirrored way i.e. column 1/160, 2/159 to 80/81. this a llows single layer pcb or glass layout. 10.2.3.2 disp_conf bit p: the p bit is used to flip the display left to right by mirroring the column data, as shown in figure 19 . this allows the display to be viewed from behind instead of front and enhances the flexibility in the assembly of equipment and avoids complicated data manipulation within the controller. table 23. screen_conf bit description bit symbol value description rs - 0 see table 10 r/w -0 7 to 1 - 0000001 fixed value 0l screen configuration 0 split screen standard connection 1 split screen mirrored connection table 24. disp_conf bit description bit symbol value description rs - 0 see table 10 r/w -0 7 to 2 - 000001 fixed value 1p display column configuration 0 column data: left to right; column data is displayed from column 1 to column 80 1 column data: right to left; column data is displayed from column 80 to column 1 0q display row configuration 0 row data: top to bottom; row data is displayed from row 1 to row 16 and icon row data in row 17 and row 18 in single line mode (sl = 1) row data is displayed from row 1 to row 8 and icon row data in row 17 1 row data: bottom to top; row data is displayed from row 16 to row 1 and icon row data in row 18 and row 17 in single line mode (sl = 1) row data is displayed from row 8 to row 1 and icon row data in row 17
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 37 of 83 nxp semiconductors pcf2119x lcd controllers/drivers bit q: the q bit flips the display top to bottom by mirroring the row data, as shown in figure 20 . combination of bit p and bit q: a combination of p and q allows the display to be rotated horizontally and vertically by 180 degree, as shown in figure 21 . this is useful for viewing the display from the opposite edge. fig 19. use of bit p fig 20. use of bit q fig 21. use of bit p and bit q 013aaa12 2 p = 0 p = 1 q = 0 q = 0 013aaa11 3 q = 0 q = 1 p = 0 p = 0 013aaa12 3 q = 0 q = 1 p = 1 p = 0
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 38 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 10.2.3.3 icon_ctl the pcf2119x can drive up to 160 icons. see figure 22 and figure 23 for cgram to icon mapping. bit im: when bit im = 0, the chip is in character mode. in the character mode characters and icons are driven (multiplex drive mode 1:18 or 1:9). the v lcd generator, if used, produces the v lcdout voltage programmed with register v a . when bit im = 1, the chip is in icon mode. in the icon mode only the icons are driven (multiplex drive mode 1:2). the v lcd generator, if used, produces the v lcdout voltage as programmed with register v b . bit ib: icon blink control is independent of the cursor/character blink function. when bit ib = 0, the icon blink is disabled. icon data is stored in cgram character 0 to 3 (4 8 5 = 160 bits for 160 icons). when bit ib = 1, the icon blink is enabled. in th is case each icon is controlled by two bits. blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter). icon states for the even phase are stored in cgram characters 0 to 3 (4 8 5 = 160 bits for 160 icons). these bits also define icon state when icon blink is not used (see ta b l e 2 7 ). icon states for the odd phase are stored in cgram character 4 to 7 (another 160 bits for the 160 icons). when icon blink is disabled cgram characters 4 to 7 may be used as normal cgram characters. table 25. icon_ctl bit description bit symbol value description rs - 0 see table 10 r/w -0 7 to 3 - 00001 fixed value 2im icon mode 0 character mode, full display 1 icon mode, only icons displayed 1ib icon blink 0 icon blink disabled 1 icon blink enabled 0dm direct mode 0off 1on table 26. normal/icon mode operation bit im mode v lcdout 0 character mode generated from v a 1 icon mode generated from v b
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 39 of 83 nxp semiconductors pcf2119x lcd controllers/drivers bit dm: when dm = 0, the chip is not in the direct mode. either the internal v lcd generator or an external voltage may be used to achieve v lcd . when dm = 1, the chip is in direct mode. the internal v lcd generator is turned off and the output v lcdout is directly connected to v dd2 (i.e. the v lcd generator supply voltage). table 27. blink effect for icons and cursor character blink parameter even phase odd phase cursor character blink block (all on) normal (display character) icons state 1; cgram character 0 to 3 state 2; cgram character 4 to 7 fig 22. cgram to icon mapping (a) col 1 to 5 12345 81 82 83 84 85 display: row 17 ? row 18 ? block of 5 columns col 6 to 10 678910 86 87 88 89 90 col 76 to 80 76 77 78 79 80 156 157 158 159 160 mgl24 9 cgram data: logic 1 of a data bit turns the icon on and logic 0 turns the icon off. character codes: bits 0 to 3 define the icon state when icon bl ink is disabled or during the even phase when icon blink is enabled. bits 4 to 7 define the icon state during the odd phas e when icon blink is enabled (not used for icons when icon blink is disabled) fig 23. cgram to icon mapping (b) mgk99 9 156-160 odd (blink) 18/76-80 0 0 0 0 0 1 1 1 icon view 0 1 1 1 1 1 1 0 0 1 1 0 1-5 odd (blink) 17/1-5 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 156-160 even 18/76-80 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 1 81-85 even 18/1-5 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 76-80 even 17/76-80 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 11-15 even 17/11-15 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 6-10 even 17/6-10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1-5 even 17/1-5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 7 6 5 4 3 2 1 0 msb lsb lsb msb msb lsb 6 5 4 3 2 1 0 4 3 2 1 0 icon no. phase row/col character codes cgram address cgram data
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 40 of 83 nxp semiconductors pcf2119x lcd controllers/drivers remark: in direct mode, no external v lcd is possible. the direct mode can be used to reduce the cu rrent consumption when the required output voltage v lcdout is close to the v dd2 supply voltage. this can be the case in icon mode or in mux 1:9 (depending on lcd liquid properties). 10.2.3.4 temp_ctl the bit-field tc[1:0] selects the temperature coefficient for the internally generated v lcdout (see ta b l e 2 9 ). 10.2.3.5 hv_gen a software configurable voltage mu ltiplier is incorp orated in the v lcd generator and can be set via the hv_gen command. the voltage multiplier control can be used to reduce current consumption by disconnecting internal voltage multiplier stages, depending on the required v lcdout output voltage (see ta b l e 3 1 ). table 28. temp_ctl bit description bit symbol value description rs - 0 see table 10 r/w -0 7 to 2 - 000100 fixed value 1 to 0 tc[1:0] 00 to 11 temperature coefficient table 29. tc[1:0] selection of v lcd temperature coefficient tc[1:0] typical value description 00 ? 0.16 %/k v lcd temperature coefficient 0 (default value) 10 ? 0.18 %/k v lcd temperature coefficient 1 01 ? 0.21 %/k v lcd temperature coefficient 2 11 ? 0.24 %/k v lcd temperature coefficient 3 table 30. hv_gen bit description bit symbol value description rs - 0 see table 10 r/w -0 7 to 2 - 010000 fixed value 1 to 0 s[1:0] 00 to 11 voltage multiplier table 31. voltage multiplier control bits s[1:0] description 00 set v lcd generator stages to 1 (2 voltage multiplier) 01 set v lcd generator stages to 2 (3 voltage multiplier) 10 set v lcd generator stages to 3 (4 voltage multiplier) 11 do not use
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 41 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 10.2.3.6 vlcd_set the v lcd value is calculated with the equation 2 on page 10 . the multiplication factor is programmed by instruction. two on-chip registers (v a and v b ) hold the multiplication factor for the character mode and the ic on mode, respectively. the generated v lcdout value is independent of v dd , allowing battery operation of the chip. v x programming: 1. send function_set instruction with bit h = 1. 2. send vlcd_set instruction to write to the voltage register: a. bit 7 = 1 and bit 6 = 0: bit 5 to bit 0 are the multiplication factor for v lcd of character mode (v a ). b. bit 7 = 1 and bit 6 = 1: bit 5 to bit 0 are the multiplication factor for v lcd of icon mode (v b ). c. bit 5 to bit 0 = 0 switches v lcd generator off (when selected). d. during ?display off?/power-down the v lcd generator is also disabled. 3. send function_set instruction with bit h = 0 to resume normal programming. table 32. vlcd_set bit description bit symbol value description rs - 0 see table 10 r/w -0 7 - 1 fixed value 6v set register v a or v b 0 set register v a 1 set register v b 5 to 0 v a or v b 000000 to 111111 factor for calculating v lcd
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 42 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 11. basic architecture 11.1 parallel interface the pcf2119x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. in 8-bit mode data is transferred as 8-bit bytes using the 8 ports db7 to db0. three further control lines e, rs and r/w are required. in 4-bit mode data is transferred in two cycles of 4 bits each using ports db7 to db4 for the transaction. the higher order bits (corresponding to range of bit 7 to bit 4 in 8-bit mode) are sent in the first cycle and the lower or der bits (bit 3 to bit 0 in 8-bit mode) in the second cycle. data transfer is complete after two 4-bit data transfers. it should be noted that two cycles are also requir ed for the busy flag check. 4- bit operation is selected by instruction (see figure 24 to figure 26 for examples of bus protocol). in 4-bit mode, ports db3 to db0 must be left open-circuit. they are pulled up to v dd internally. fig 24. 4-bit transfer example mga80 4 rs e db7 r/w db6 db5 db4 instruction write busy flag and address counter read data register read ir7 ir3 bf ac3 dr7 dr3 ir6 ir2 ac6 ac2 dr6 dr2 ir5 ir1 ac5 ac1 dr5 dr1 ir4 ir0 ac4 ac0 dr4 dr0
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 43 of 83 nxp semiconductors pcf2119x lcd controllers/drivers ir7, ir3: instruction 7th, 3rd bit. ac3: address counter 3rd bit. d7, d3: data 7th, 3rd bit. fig 25. an example of 4-bit data transfer timing sequence mga80 5 rs e internal db7 r/w internal operation ir7 ir3 ac3 d7 d3 not busy ac3 busy instruction write busy flag check busy flag check instruction write fig 26. example of busy flag checking timing sequence mga80 6 instruction write busy flag check busy flag check busy flag check instruction write internal operation rs e internal db7 r/w data busy busy not busy data
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 44 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 11.2 i 2 c-bus interface the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are the serial data line (sda) and the serial clock line (scl). both lines must be connected to a positive supply via pull- up resistors. data transfer may be initiated only when the bus is not busy. each byte of eight bits is followed by an acknowledge bit. a slave receiver which is addressed must generate an acknowledg e after the reception of each byte. also a master receiver must generate an ac knowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold time s must be taken into consideration). a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. fig 27. system configuration fig 28. bit transfer fig 29. definition of start and stop conditions mga80 7 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver mbc62 1 data line stable; data valid change of data allowed sda scl mbc62 2 sda scl p stop condition sda scl s start condition
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 45 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 11.2.1 i 2 c-bus protocol two i 2 c-bus slave addresses (0111 010 and 0111 011) are reserved for the pcf2119x.the entire i 2 c-bus slave address byte is shown in ta b l e 3 3 . bit 1 of the slave address byte, that a pcf2 119x will respond to, is defined by the level tied to its sa0 input (v ss for logic 0 and v dd for logic 1). before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always ca rried out with the first byte transmitted after the start procedure. the i 2 c-bus configuration for the different pcf21 19x read and write cycles is shown in figure 31 to figure 33 . the slow down feature of the i 2 c-bus protocol (receiver holds scl line low during internal operations) is not used in the pcf2119x. 11.2.2 i 2 c-bus definitions definitions: ? transmitter: the device which sends the data to the bus. ? receiver: the device which receives the data from the bus. ? master: the device which initia tes a transfer, generates clock signals and terminates a transfer. ? slave: the device addressed by a master. ? multi-master: more than one master can atte mpt to control the bus at the same time without corrupting the message. fig 30. acknowledgement on the i 2 c-bus mbc60 2 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master table 33. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb 011101sa0r/w
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 46 of 83 nxp semiconductors pcf2119x lcd controllers/drivers ? arbitration: procedure to ensure that if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted. ? synchronization: procedure to synchronize t he clock signals of two or more devices. fig 31. master transmits to slave receiver; write mode mgk89 9 s a 0 s p 011101 0a slave address control byte a 1 co data byte a control byte a r/w 0 co update data pointer 1 byte n 0 bytes 2n 0 bytes data byte a acknowledgement from pcf2119x rs rs last data byte is a dummy byte (may be omitted). fig 32. master reads after setting word address; writes word address, set rs; read_data mgg003 s a 0 s 011101 0 a slave address control byte a 1 co data byte a control byte a r/w 0 co co update data pointer update data pointer 1 byte n 0 bytes n bytes last byte 2n 0 bytes data byte (1) a acknowledgement s a 0 s 1a data byte a 1 p slave address data byte acknowledgement acknowledgement no acknowledgement r/w rs rs
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 47 of 83 nxp semiconductors pcf2119x lcd controllers/drivers fig 33. master reads slave immediately afte r first byte; read mode (rs previously defined) 013aaa155 co s a 0 s 1a a 1 p data byte last byte n bytes update data pointer update data pointer no acknowledgement from master acknowledgement from master acknowledgement from pcf2119x data byte slave address r/w
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 48 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 12. internal circuitry table 34. device protection circuits symbol pin internal circuit v dd1 1 to 6 v dd2 7 to 14 v dd3 15 to 18 v ss1 22 to 29 v ss2 30 to 35 v lcdsense 36 v lcdin 44 to 49 v lcdout 37 to 43 scl 151 to 152 sda 156 to 157 osc 168 pd 155 por 154 t1 20 t2 21 t3 153 e19 rs 159 r/w 158 db0 to db7 160 to 167 r1 to r18 58, 57 to 51, 142 to 149, 59, 100, 141 c1 to c80 140 to 101, 99 to 60 013aaa16 9 v dd1 v ss1 013aaa17 0 v dd2 v ss2 v ss1 013aaa17 1 v dd3 v ss1 013aaa17 2 v ss2 v ss1 013aaa17 3 v ss1 013aaa17 4 v dd1 v ss1 013aaa175 v lcdin v ss1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 49 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 13. limiting values [1] pass level; human body model (hbm) according to ref. 5 ? jesd22-a114 ? . [2] pass level; machine model (mm), according to ref. 6 ? jesd22-a115 ? . [3] pass level; latch-up testing according to ref. 7 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [4] according to the nxp store and transport requirements (see ref. 9 ? nx3-00092 ? ) the devices have to be stored at a temperature of +8 c to +45 c and a humidity of 25 % to 75 %. for long term storage products deviant conditions are described in that document. table 35. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd1 supply voltage 1 logic ? 0.5 +6.5 v v dd2 supply voltage 2 v lcd generator ? 0.5 +4.5 v v dd3 supply voltage 3 v lcd lcd supply voltage ? 0.5 +7.5 v v i input voltage v dd related ? 0.5 +6.5 v v lcd related ? 0.5 +7.5 v i i input current dc level ? 10 +10 ma i o output current dc level ? 10 +10 ma i dd supply current ? 50 +50 ma i ss ground supply current ? 50 +50 ma i dd(lcd) lcd supply current ? 50 +50 ma p tot total power dissipation - 400 mw p o output power dissipation per output -100 mw v esd electrostatic discharge voltage hbm [1] - 3000 v mm [2] - 300 v i lu latch-up current [3] -200 ma t stg storage temperature [4] ? 65 +150 c t amb ambient temperature operating device ? 40 +85 c
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 50 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 14. static characteristics table 36. static characteristics v dd1 = 1.5 v to 5.5 v; v dd2 =v dd3 = 2.2 v to 4.0 v; v ss =0v;v lcd = 2.2 v to 6.5 v; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd1 supply voltage 1 logic 1.5 - 5.5 v v dd2 supply voltage 2 internal v lcd generation; v lcd >v dd2 =v dd3 2.2 - 4.0 v v dd3 supply voltage 3 v lcd lcd supply voltage pins v lcd , v lcdin , v lcdout 2.2 - 6.5 v ground supply current using external v lcd [1] i ss ground supply current - 70 120 a v dd =3v; v lcd =5v [2] -3580 a icon mode; v dd =3v; v lcd =2.5v [2] -2545 a power-down mode; v dd =3v; v lcd =2.5v; db7todb0, rs and r/w = 1; osc = 0; pd = 1 -0.55 a ground supply current using internal v lcd [1] [3] i ss ground supply current - 190 400 a v dd =3v; v lcd =5v [2] - 135 400 a icon mode; v dd =2.5v; v lcd =2.5v [2] -85- a logic v i input voltage ? 0.5 - v dd1 +0.5 v v il low-level input voltage v ss1 -0.3v dd1 v v ih high-level input voltage 0.7v dd1 -v dd1 v oscillator input; pin osc v il low-level input voltage v ss1 -v dd1 ? 1.2 v v ih high-level input voltage v dd1 ? 0.1 - v dd1 v data bus; pins db7 to db0 i ol low-level output curr ent output sink current; v ol =0.4v; v dd1 =5v 1.6 4 - ma i oh high-level output current output source current; v oh =4v; v dd1 =5v 18- ma i pu pull-up current v i =v ss1 0.04 0.15 1 a i l leakage current v i =v dd1, 2, 3 or v ss1, 2 ? 1- +1 a i 2 c-bus; pins sda and scl inputs: pins sda and scl v i input voltage [4] ? 0.5 - 5.5 v v il low-level input voltage 0 - 0.3v dd1 v v ih high-level input voltage 0.7v dd1 -5.5v i li input leakage current v i =v dd1, 2, 3 or v ss1, 2 ? 1- +1 a
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 51 of 83 nxp semiconductors pcf2119x lcd controllers/drivers [1] lcd outputs are open-circuit; inputs at v dd or v ss ; bus inactive. [2] t amb =25 c; f osc = 200 khz. [3] lcd outputs are open-circuit; v lcd generator is on; load current i lcd =5 a. [4] the i 2 c-bus interface of pcf2119x is 5 v tolerant. [5] resistance of output pins (r1 to r18 and c1 to c80) with a load current of 10 a; outputs measured one at a time; external lcd supply v lcd =3v; v dd1 =v dd2 =v dd3 =3v. [6] lcd outputs open-circui t; external lcd supply. c i input capacitance - 5 - pf output: pin sda i ol low-level output current output sink current v ol =0.4v; v dd1 >2v 3 - - ma v ol =0.2v dd1 ; v dd1 <2v 2 - - ma lcd outputs r o output resistance row output, pins r1 to r18 [5] -1030k column output, pins c1 to c80 [5] -1540k v bias bias voltage variation on pins r1 to r18 and c1 to c80 [6] -20130mv v lcd lcd voltage variation t amb =25 c [3] v lcd <3v - - 160 mv v lcd <4v - - 200 mv v lcd <5v - - 260 mv v lcd <6v - - 340 mv table 36. static characteristics ?continued v dd1 = 1.5 v to 5.5 v; v dd2 =v dd3 = 2.2 v to 4.0 v; v ss =0v;v lcd = 2.2 v to 6.5 v; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 52 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 15. dynamic characteristics table 37. dynamic characteristics v dd1 = 1.5 v to 5.5 v; v dd2 =v dd3 = 2.2 v to 4.0 v; v ss =0v; v lcd = 2.2 v to 6.5 v; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit clock and oscillator f fr(lcd) lcd frame frequency internal clock; v dd =5.0v 45 95 147 hz f osc oscillator frequency not available at any pin 140 250 450 khz f osc(ext) external oscillator frequency 140 - 450 khz t d(startup)(osc) start-up delay time on pin osc oscillator, after power-down [1] -200300 s timing characteristics of parallel interface [2] write operation (writing data from microcontroller to pcf2119x); see figure 34 t cy(en) enable cycle time 500 - - ns t w(en) enable pulse width 220 - - ns t su(a) address set-up time 50 - - ns t h(a) address hold time 25 - - ns t su(d) data input set-up time 60 - - ns t h(d) data input hold time 25 - - ns read operation (reading data from pcf2119x to microcontroller); see figure 35 t cy(en) enable cycle time 500 - - ns t w(en) enable pulse width 220 - - ns t su(a) address set-up time 50 - - ns t h(a) address hold time 25 - - ns t d(dv) data input valid delay time v dd1 > 2.2 v - - 150 ns v dd1 > 1.5 v - - 250 ns t h(d) data input hold time 20 - 100 ns timing characteristics of i 2 c-bus interface [2] ; see figure 36 f scl scl clock frequency - - 400 khz t low low period of the scl clock 1.3 - - s t high high period of the scl clock 0.6 - - s t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns t r rise time of both sda and scl signals [1] [3] 15 + 0.1 c b - 300 ns t f fall time of both sda and scl signals [1] [3] 15 + 0.1 c b - 300 ns c b capacitive load for each bus line --400pf t su;sta set-up time for a repeated start condition 0.6 - - s t hd;sta hold time (repeated) start condition 0.6 - - s
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 53 of 83 nxp semiconductors pcf2119x lcd controllers/drivers [1] tested on sample base. [2] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . [3] c b = total capacitance of one bus line in pf. t su;sto set-up time for stop condition 0.6 - - s t sp pulse width of spikes that must be suppressed by the input filter --50ns t buf bus free time between a stop and start condition 1.3 - - s table 37. dynamic characteristics ?continued v dd1 = 1.5 v to 5.5 v; v dd2 =v dd3 = 2.2 v to 4.0 v; v ss =0v; v lcd = 2.2 v to 6.5 v; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit fig 34. parallel bus write operation sequence; writing data from microcontroller to pcf2119x fig 35. parallel bus read operation sequence; writing data from pcf2119x to microcontroller rs e db0 to db7 v ih v il v il v il v ih v il v ih v il v ih v il v ih v il v ih v il v il t cy(en) t su(a) t w(en) t h(a) t h(a) t h(d) t su(d) valid data mbk47 4 r/ w rs e db0 to db7 v ih v ih v ih v il v ih v il v oh v ol v oh v ol v ih v il v ih v il v il t cy(en) t su(a) t w(en) t h(a) t h(a) t h(d) t d(dv) mbk47 5 r/ w
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 54 of 83 nxp semiconductors pcf2119x lcd controllers/drivers fig 36. i 2 c-bus timing diagram sda mga72 8 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 55 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 16. application information 16.1 general application information the required minimum value for the external capacitors in an application with the pcf2119x are: c ext from pins v lcd to v ss = 100 nf and for pins v dd to v ss =470nf. higher capacitor values are recommended for ripple reduction. for cog applications the recommended ito tra ck resistance is to be minimized for the i/o and supply connections. optimized values for these tracks are below 50 for the supply and below 100 for the i/o connections. higher track resistance reduce performance and increase current consumption. to avoid accidental triggering of power-on reset (por) (especially in co g applications), the supplies must be adequately decoupled. depending on power supply quality, v dd1 may have to be risen above the specified minimum. when external lcd supply voltage is supplied, v lcdout should be left open-circuit to avoid any stray current, and v lcdin must be connected to v lcdsense . the pcf2119x i 2 c-bus interface is compatible with systems, where the i 2 c pull-up resistors are connected to a 5 v 10 % supply. 16.2 power supply connections for internal v lcd generation drawings are showing alternative circuits. decoupling capacitors are not shown in the drawings. fig 37. recommended v dd connections for internal v lcd generation the value of the capacitor should be at least 100 nf. fig 38. recommended v lcd connections for internal v lcd generation v dd1 v dd2 v dd3 v ss1 v ss2 gnd 1.5 v to 5.5 v 2.2 v to 4.0 v 013aaa11 4 v dd1 v dd2 v dd3 v ss1 v ss2 gnd 2.2 v to 4.0 v 013aaa11 5 013aaa11 6 v ss2 v lcdin v lcdout v lcdsense
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 56 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 16.3 power supply connections for external v lcd generation remark: when using an external v lcd , the internal v lcd generator must never be switched on and direct mode must be avoided otherwise damages will occur. 16.4 information about v lcd connections v lcdin ? this input is used for generating the 5 lcd bias levels. it is the power supply for the bias level buffers. v lcdout ? this is the v lcd output if v lcd is generated internally. in this case pin v lcdout must be connected to v lcdin and to v lcdsense . if v lcd is generated externally, v lcdout must be left unconnected. v lcdsense ? this input is used for the voltage multiplier?s regulation circuitry. when using the internal v lcd generation, this pin must be connected to v lcdout and v lcdin . when using an external v lcd supply it must be connected to v lcdin only. 16.5 reducing current consumption reducing current consumption can be achi eved by one of the options given in ta b l e 3 8 . when v lcd lies outside the v dd range and must be generated, it is usually more efficient to use the on-chip v lcd generator than an external regulator. drawings are showing alternative circuits. decoupling capacitors are not shown in the drawings. fig 39. recommended v dd connections for external v lcd generation the value of the capacitor should be at least 100 nf. fig 40. recommended v lcd connections for external v lcd generation v dd1 v dd2 v dd3 v ss1 v ss2 gnd 1.5 v to 5.5 v 2.2 v to 4.0 v 013aaa11 4 gnd 013aaa11 7 v dd1 v dd2 v dd3 v ss1 v ss2 2.2 v to 4.0 v 013aaa11 8 v ss2 v lcdin v lcdout v lcdsense n.c. v lcd(ext)
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 57 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 16.6 charge pump characteristics typical graphs of the total power consumption of the pcf2119x using the internal charge pump are illustrated in figure 41 , figure 42 and figure 43 . the graphs were obtained under the following conditions: ? t amb = 25 c ? v dd1 = v dd2 = v dd3 = 2.2 v (minimum), 2.7 v (typical) and 4.0 v (maximum) ? normal mode ? f osc = internal oscillator ? multiplex drive mode 1:18 ? typical current load for i lcd = 10 a. for each multiplication factor there is a se parate line. the line ends where it is not possible to get a higher voltage under its conditions (a higher multiplication factor is needed to get higher voltages). connecting different displays may result in di fferent current consumption. this affects the efficiency and the optimum multiplication factor to be used to generate a certain output voltage. table 38. reducing current consumption original mode alternative mode character mode icon mode (control bit im) display on display off (control bit d) v lcd generator operating direct mode any mode power-down mode (pin pd) (1) 2 multiplication factor. (2) 3 multiplication factor. (3) 4 multiplication factor. fig 41. typical charge pum p characteristics (a), v dd =2.2v v lcd (v) 1.25 7.25 5.75 4.25 2.75 mgw573 0 300 200 100 400 i dd ( a) (1) (2) (3)
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 58 of 83 nxp semiconductors pcf2119x lcd controllers/drivers (1) 2 multiplication factor. (2) 3 multiplication factor. (3) 4 multiplication factor. fig 42. typical charge pum p characteristics (b), v dd =2.7v (1) 2 multiplication factor. (2) 3 multiplication factor. (3) 4 multiplication factor. fig 43. typical charge pum p characteristics (c), v dd =4.0v mgw574 v lcd (v) 1.25 7.25 5.75 4.25 2.75 100 200 300 i dd ( a) 0 (1) (2) (3) mgw575 v lcd (v) 1.25 7.25 5.75 4.25 2.75 100 200 300 i dd ( a) 0 (1) (2) (3)
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 59 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 16.7 interfaces fig 44. typical application using para llel interface, 4 or 8 bit bus possible fig 45. application using i 2 c-bus interface 013aaa11 9 pcf2119x 16 4,8 c1 to c80 80 osc rs db7 to db4 db3 to db0 e 470 nf 100 nf r1 to r16 v ss r/w 2 r17, r18 v dd v dd v lcd v ss 2 16 character lcd display plus 160 icons v dd v dd scl sda i 2 c master, microcontroller pcf2119x 2 16 character lcd display plus 160 icons 16 c1 to c80 80 2 osc scl sda db3/sao 470 nf 100 nf r17, r18 r1 to r16 v dd v dd v ss v dd v lcd v ss pcf2119x 1 32 character lcd display plus 160 icons 16 c1 to c80 80 2 osc scl sda db3/sao 470 nf 100 nf r17, r18 r1 to r16 v ss v dd v ss v dd v lcd v ss mgk89 8
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 60 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 16.8 connections wi th lcd modules fig 46. connecting pcf2119x with 2 16 character lcd pcf2119x 8 80 8 r17 r1 to r8 c1 to c80 r9 to r16 r18 icons 013aaa12 0 character row 1 character row 2 fig 47. connecting pcf2119x with 1 32 character lcd pcf2119x 8 80 8 r17 r1 to r8 c1 to c80 r9 to r16 r18 icons 013aaa12 1 icons c1 to c80 character row 1 character row 1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 61 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 16.9 4-bit operation, 1-line display using external reset the program must set functions prior to a 4-bit operation (see ta b l e 3 9 ). when power is turned on, 8-bit operation is automatically selected and the pcf2119x attempts to perform the first write as an 8-bit operation. since nothing is connected to ports db0 to db3, a rewrite is then required. however, since one operation is complete d in two accesses of 4-bit operation, a rewrite is required to set the functions (see table 39 step 3). thus, db4 to db7 of the function_set are written twice. 16.10 8-bit operation, 1-line display using external reset ta b l e 4 0 and table 41 show an example of a 1-line display in 8-bit operation. the pcf2119x functions must be set by the function_set instructio n prior to display. since the ddram can store data for 80 characters, the ram can be used for advertising displays when combined with display shift operation. since the display shift operation changes display position only and the ddram contents remain unchanged, display data entered first can be displayed when the return_home operation is performed. table 39. 4-bit operation, 1-line display exam ple; using external reset (character set ?a?) step instruction display operation rs r/w db7 db6 db5 db4 1 power supply on initialized by the external reset; no display appears 2 function_set sets to 4-bit operation; in this instance operation is handled as 8-bit by initialization and only this instruction completes with one write 000010 3 function_set sets to 4-bit operation, selects 1-line display and v lcd =v 0 ; 4-bit operation starts from this point and resetting is needed 000010 000000 4 display_ctl turns display and cursor on; entire display is blank after initialization 000000 001110 5 entry_mode_set sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the ddram or cgram; display is not shifted 000000 000110 6 write_data to cgram/ddram writes ?p?; the ddram has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right 100101 p 100000 table 40. 8-bit operation, 1-line display exam ple; using external reset (character set ?a?) step instruction display operation rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 power supply on initialized by the external reset; no display appears 2 function_set sets to 8-bit operation, selects 1-line display and v lcd =v 0 0000110000 3 display_ctl turns on display and cursor; entire display is blank after initialization 0000001110
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 62 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 4 entry_mode_set sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the ddram/cgram; display is not shifted 0000000110 5 write_data to cgram/ddram writes ?p?; the ddram has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right 1001010000 p 6 write_data to cgram/ddram writes ?h? 1001001000 ph 7 to 10 : philip writes ?ilip? 11 write_data to cgram/ddram writes ?s? 1001010011 philips 12 entry_mode_set sets mode for display shift at the time of write 0000000111 philips 13 write_data to cgram/ddram writes space 1000100000 hilips 14 write_data to cgram/ddram writes ?m? 1001001101 ilips m 15 to 19 : microk writes ?icrok? 20 write_data to cgram/ddram writes ?o? 1001001111 microko 21 curs_disp_shift shifts only the cursor position to the left 0000010000 microk o 22 curs_disp_shift shifts only the cursor position to the left 0000010000 micro k o 23 write_data to cgram/ddram writes ?c? correction; display moves to the left 1001000011 icroc o 24 curs_disp_shift shifts the display and cursor to the right 0000011100 microc o 25 curs_disp_shift shifts only the cursor to the right 0000010100 microco 26 write_data to cgram/ddram writes ?m? 1001001101 icrocom 27 return_home returns both display and cursor to the original position (address 0) 0000000010 p hilips m table 40. 8-bit operation, 1-line display exam ple; using external reset (character set ?a?) ?continued step instruction display operation rs r/w db7 db6 db5 db4 db3 db2 db1 db0
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 63 of 83 nxp semiconductors pcf2119x lcd controllers/drivers table 41. 8-bit operation, 1-line display and icon example; using external reset (character set ?a?) step instruction display operation rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 power supply on initialized by the external reset; no display appears 2 function_set sets to 8-bit operation, selects 1-line display and v lcd =v 0 0000110000 3 display_ctl turns on display and cursor; entire display is blank after initialization 0000001110 4 entry_mode_set sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the dd/cgram; display is not shifted 0000000110 5 set_cgram sets the cgram address to position of character 0; the cgram is selected 0001000000 6 write_data to cgram/ddram writes data to cgram for icon even phase; icons appears 1000001010 7 : 8 set_cgram sets the cgram address to position of character 4; the cgram is selected 0001110000 9 write_data to cgram/ddram writes data to cgram for icon odd phase 1000001010 10 : 11 function_set sets bit h = 1 0000110001 12 icon_ctl icons blink 0000001010 13 function_set sets bit h = 0 0000110001 14 set_ddram sets the ddram address to the first position; ddram is selected 0010000000 15 write_data to cgram/ddram writes ? p?; the cursor is incremented by 1 and shifted to the right 1001010000 p 16 write_data to cgram/ddram writes ?h? 1001001000 ph 17 to 21 : philips writes ?ilips? 22 return_home returns both display and cursor to the original position (address 0) 0000000010 p hilips
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 64 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 16.11 8-bit operation, 2-line display for a 2-line display the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. thus, if there are only 8 characters in the first line, the ddram address must be set after the 8th character is completed (see table 42 ). it should be noted that both lines of the display are always shifted together; data does not shift from one line to the other. table 42. 8-bit operation, 2-line display exam ple; using external reset (character set ?a?) instruction step rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display operation 1 power supply on initialized by the external reset; no display appears 2 function_set sets to 8-bit operation; selects 2-line display and v lcd generator off 0000110100 3 display mode on/off control turns on display and cursor; entire display is blank after initialization 0000001110 4 entry_mode_set sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the cg/ddram; display is not shifted 0000000110 5 write_data to cgram/ddram writes ?p?; the ddram has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right 1001010000 p 6 to 10 : philip writes ?hilip? 11 write_data to cgram/ddram writes ?s? 1001010011 philips 12 set_ddram sets ddram address to position the cursor at the head of the 2nd line 0011000000 philips 13 write_data to cgram/ ddram writes ?m? 1001001101 philips m 14 to 18 : philips microc writes ?icroc? 19 write_data to cgram/ddram writes ?o? 1001001111 philips microco 20 write_data to cgram/ddram sets mode for display shift at the time of write 0000000111 philips microco 21 write_data to cgram/ddram writes ?m?; display is shifted to the left; the first and second lines shift together 1001001101 hilips icrocom
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 65 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 16.12 i 2 c-bus operation, 1-line display a control byte is require d with most commands (see ta b l e 4 3 ). 22 : : 23 return_home returns both display and cursor to the original position (address 0) 0000000010 p hilips microcom table 42. 8-bit operation, 2-line display exam ple; using external reset (character set ?a?) ?continued instruction step rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display operation table 43. example of i 2 c-bus operation; 1-line display (using external reset, assuming pin sa0 = v ss ) [1] step i 2 c-bus byte display operation 1i 2 c-bus start initialized; no display appears 2 slave address for write during the acknowledge cycle sda will be pulled-down by the pcf2119x sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w ack 011101001 3 send a control byte for function_set control byte sets rs for following data bytes cors000000ack 000000001 4 function_set selects 1-line display and v lcd =v 0 ; scl pulse during acknowledge cycle starts execution of instruction db7 db6 db5 db4 db3 db2 db1 db0 ack 001x00001 5 display_ctl turns on display and cursor; entire display shows character code 20h (blank in ascii-like character sets) db7 db6 db5 db4 db3 db2 db1 db0 ack 000011101 6 entry_mode_set sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the ddram or cgram; display is not shifted db7 db6 db5 db4 db3 db2 db1 db0 ack 000001101 7i 2 c-bus start for writing data to ddram, rs must be set to 1; therefore a control byte is needed 8 slave address for write sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w ack 011101001 9 send a control byte for write_data cors000000ack 010000001 10 write_data to ddram writes ?p?; the ddram has been selected at power-on; the cursor is incremented by 1 and shifted to the right db7 db6 db5 db4 db3 db2 db1 db0 ack p 010100001 11 write_data to ddram writes ?h? db7 db6 db5 db4 db3 db2 db1 db0 ack ph 010010001 12 to 15 : philip writes ?ilip?
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 66 of 83 nxp semiconductors pcf2119x lcd controllers/drivers [1] x = don?t care. [2] sda is left at high-impedance by the microcontroller during the read acknowledge. 16 write_data to ddram writes ?s? db7 db6 db5 db4 db3 db2 db1 db0 ack philips 010100111 17 optional l 2 c-bus stop philips 18 i 2 c-bus start philips 19 slave address for write sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w ack philips 011101001 20 control byte cors000000ack philips 100000001 21 return_home sets ddram address 0 in address counter (also returns shifted display to original position; ddram contents unchanged); this instruction does not update the data register db7 db6 db5 db4 db3 db2 db1 db0 ack p hilips 000000101 22 i 2 c-bus start p hilips 23 slave address for read during t he acknowledge cycle the content of the data register is loaded into the internal i 2 c-bus interface to be shifted out; in the previous instruction neither a ?set address? nor a read_data has been performed; therefore the content of the data register was unknown; bit r/w has to be set to logic 1 while still in i 2 c-write mode sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w ack p hilips 011101011 24 control byte for read ddram content will be read from following instructions cors000000ack p hilips 011000001 25 read_data: 8 scl + master acknowledge [2] 8 scl; content loaded into interface during previous acknowledge cycle is shifted out over sda; msb is db7; during master acknowledge content of ddram address 01 is loaded into the i 2 c-bus interface db7 db6 db5 db4 db3 db2 db1 db0 ack p hilips xxxxxxxx0 26 read_data: 8 scl + master acknowledge [2] 8 scl; code of letter ?h? is read first; during master acknowledge code of ?i? is loaded into the i 2 c-bus interface db7 db6 db5 db4 db3 db2 db1 db0 ack p hilips 010010000 27 read_data: 8 scl + no master acknowledge [2] no master acknowledge; after the content of the i 2 c-bus interface register is shifted out no internal action is performed; no new data is loaded to the interface register, data register is not updated, address counter is not incremented and cursor is not shifted db7 db6 db5 db4 db3 db2 db1 db0 ack p hilips 010010011 28 i 2 c-bus stop p hilips table 43. example of i 2 c-bus operation; 1-line display (using external reset, assuming pin sa0 = v ss ) [1] ?continued step i 2 c-bus byte display operation
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 67 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 16.13 initialization [1] x = don?t care. table 44. initialization by instruction, 8-bit interface ( [1] ) step instruction description rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 power-on or unknown state 2 wait 2 ms after internal reset has been applied 3 function_set interface is 8 bits long; bf cannot be checked before this instruction 000011xxxx 4wait 2ms 5 function_set interface is 8 bits long; bf cannot be checked before this instruction 000011xxxx 6 wait more than 40 s 7 function_set interface is 8 bits long; bf cannot be checked before this instruction 000011xxxx bf can be checked after the following instructions; when bf is not checked, the waiting time between instructions is the specified instruction time (see ta b l e 11 ) 8 function_set (interface is 8 bits long) specify number of display lines 0000110m0h 9 display_ctl display off 0000001000 10 clear_display 0000000001 11 entry_mode_set 00000001i_ds 12 initialization ends
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 68 of 83 nxp semiconductors pcf2119x lcd controllers/drivers table 45. initialization by instruction, 4-bit interface; not applicable for i 2 c-bus operation step instruction description rs r/w db7 db6 db5 db4 1 power-on or unknown state 2 wait 2 ms after internal reset has been applied 3 function_set interface is 8 bits long; bf cannot be checked before this instruction 000011 4wait 2ms 5 function_set interface is 8 bits long; bf cannot be checked before this instruction 000011 6 wait more than 40 s 7 function_set interface is 8 bits long; bf cannot be checked before this instruction 000011 bf can be checked after the following instructi ons; when bf is not checked, the waiting time between instructions is the specified instruction time (see ta b l e 11 ) 8 function_set 000010set interface to 4bit long interface is 8 bit long 9 function_set 000010set interface to 4bits long 000m0hspecify number of display line 10 display_ctl 000000 001000display off 11 clear_display 000000 000001 12 entry_mode_set 000000 0001i_ds : 13 initialization ends
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 69 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 16.14 user defined characters and symbols up to 16 user defined characters may be stored in the cgram. the content of the cgram is lost during power-do wn, therefore the cgram has to be rewritten after every power-on. below some source code is printed, which shows how a user defined character is defined - in this case the euro currency sign. the display used is a 2 lines by 16 characters display and the interface is the i 2 c-bus: // write a user defined character into the cgram starti2c(); // pcf2119 slave address for write, sa0 is connected to vdd sendi2caddress(0x76); // msb (continuation bit co) = 0, more than one byte may follow. bit6, rs=0, next byte // is command byte i2c_write(0x00); // 2 lines x 16, 1/18 duty, basic instruction set. next byte will be another command. i2c_write(0x24); // set cgram address to 0 i2c_write(0x40); // repeated start condition starti2c(); sendi2caddress(0x76); // rs=1, next byte is a data byte i2c_write(0x40); // here the data bytes to define the character // behind the write commands the 5x8 dot matrix is shown, the 1 represents a on pixel. // the euro currency character can be recognized by the 0/1 pattern (see figure 48 ) i2c_write(0x06); // 00110 i2c_write(0x09); // 01001 i2c_write(0x08); // 01000 i2c_write(0x1e); // 11110 i2c_write(0x1e); // 11110 i2c_write(0x08); // 01000 i2c_write(0x09); // 01001 fig 48. user defined euro currency sign 00 0 000 0000 0 0 0000 000 00 0 013aaa14 4 11 11 1 11 1 11 1 1 1 11 1 1 1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 70 of 83 nxp semiconductors pcf2119x lcd controllers/drivers i2c_write(0x06); // 00110 i2c_stop(); // until here the definition of the character and writing it into the cgram. now it // still needs to be displayed. see below. // pcf2119, setting of proper display modes starti2c(); // pcf2119 slave address for write, sa0 is connected to vdd sendi2caddress(0x76); // msb (continuation bit co) = 0, more than one byte may follow. bit6, rs=0, next byte // is command byte i2c_write(0x00); // 2 lines x 16, 1/18 duty, extended instruction set. next byte will be another // command. i2c_write(0x25); // set display configuration to right to left, column 80 to 1. row data displ. top to // bottom,1 to 16. i2c_write(0x06); // set to character mode, full display, icon blink disabled i2c_write(0x08); // set voltage multiplier to 2 i2c_write(0x40); // set vlcd and store in register va i2c_write(0xa0); // change from extended instruction set to basic instruction set i2c_write(0x24); // display control: set display on, cursor off, no blink i2c_write(0x0c); // entry mode set, increase ddram after access, no shift i2c_write(0x06); // return home, set ddram address 0 in address counter i2c_write(0x02); // clear entire display, set ddram address to 0 in address counter i2c_write(0x01); // repeated start condition because rs needs to be changed from 0 to 1 starti2c(); sendi2caddress(0x76); // rs=1, next byte is data i2c_write(0x40); // write the character at address 0, which is the previously defined euro currency // character i2c_write(0x00); i2c_stop();
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 71 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 17. bare die outline fig 49. bare die outline of pcf2119x references outline version european projection issue date iec jedec jeita pcf2119x pcf2119x_do 09-07-16 09-08-03 unit mm max nom min 0.380 0.0225 0.0175 0.0125 7.59 1.71 0.070 0.350 a (1) dimensions note 1. dimension not drawn to scale b are die: 168 bumps; 7.59 x 1.71 x 0.38 mm pcf2119 x a 1 (1) b (1) 0.050 b 1 (1) 0.100 dee (1) e 1 (1) l (1) 0.090 0 2.5 5 mm scale z detail z a a 1 detail x e b detail y e 1 l b 1 x y e d 151 150 149 126 125 100 75 74 50 155 160 168 10 19 22 34 35 49 1 pc2119-2 y x 0 0 am1 am3 am4 am1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 72 of 83 nxp semiconductors pcf2119x lcd controllers/drivers table 46. pin location all x and y coordinates are referenced to the center of the ch ip (dimensions in m). symbol pin x y description v dd1 1 +745 ? 274 logic supply voltage 1 v dd1 2 +745 ? 204 v dd1 3 +745 ? 134 v dd1 4 +745 ? 64 v dd1 5 +745 +6 v dd1 6 +745 +76 v dd2 7 +745 +146 v lcd generator supply voltage 2 v dd2 8 +745 +216 v dd2 9 +745 +286 v dd2 10 +745 +356 v dd2 11 +745 +426 v dd2 12 +745 +496 v dd2 13 +745 +566 v dd2 14 +745 +636 v dd3 15 +745 +706 v dd3 16 +745 +776 v dd3 17 +745 +846 v dd3 18 +745 +916 e 19 +745 +986 data bus clock input t1 20 +745 +1196 test pin 1 t2 21 +745 +1406 test pin 2 v ss1 22 +745 +1616 ground 1 v ss1 23 +745 +1686 v ss1 24 +745 +1756 v ss1 25 +745 +1826 v ss1 26 +745 +1896 v ss1 27 +745 +1966 v ss1 28 +745 +2036 v ss1 29 +745 +2106 v ss2 30 +745 +2176 ground 2 v ss2 31 +745 +2246 v ss2 32 +745 +2316 v ss2 33 +745 +2386 v ss2 34 +745 +2456 v ss2 35 +745 +2666 v lcdsense 36 +745 +2736 input for voltage multiplier regulation v lcdout 37 +745 +2806 v lcd output v lcdout 38 +745 +2876 v lcdout 39 +745 +2946 v lcdout 40 +745 +3016
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 73 of 83 nxp semiconductors pcf2119x lcd controllers/drivers v lcdout 41 +745 +3086 v lcd output v lcdout 42 +745 +3156 v lcdout 43 +745 +3226 v lcdin 44 +745 +3296 input for generation of lcd bias levels v lcdin 45 +745 +3366 v lcdin 46 +745 +3436 v lcdin 47 +745 +3506 v lcdin 48 +745 +3576 v lcdin 49 +745 +3646 dummy (v ss1 )50 ? 745 +3576 dummy r8 51 ? 745 +3506 lcd row driver output r7 52 ? 745 +3436 r6 53 ? 745 +3366 r5 54 ? 745 +3296 r4 55 ? 745 +3226 r3 56 ? 745 +3156 r2 57 ? 745 +3086 r1 58 ? 745 +3016 r17 59 ? 745 +2946 c80 60 ? 745 +2876 lcd column driver output c79 61 ? 745 +2806 c78 62 ? 745 +2736 c77 63 ? 745 +2666 c76 64 ? 745 +2596 c75 65 ? 745 +2526 c74 66 ? 745 +2456 c73 67 ? 745 +2386 c72 68 ? 745 +2316 c71 69 ? 745 +2246 c70 70 ? 745 +2176 c69 71 ? 745 +2106 c68 72 ? 745 +2036 c67 73 ? 745 +1966 c66 74 ? 745 +1896 c65 75 ? 745 +1756 c64 76 ? 745 +1686 c63 77 ? 745 +1616 c62 78 ? 745 +1546 c61 79 ? 745 +1476 c60 80 ? 745 +1406 table 46. pin location ?continued all x and y coordinates are referenced to the center of the ch ip (dimensions in m). symbol pin x y description
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 74 of 83 nxp semiconductors pcf2119x lcd controllers/drivers c59 81 ? 745 +1336 lcd column driver output c58 82 ? 745 +1266 c57 83 ? 745 +1196 c56 84 ? 745 +1126 c55 85 ? 745 +1056 c54 86 ? 745 +986 c53 87 ? 745 +916 c52 88 ? 745 +846 c51 89 ? 745 +776 c50 90 ? 745 +706 c49 91 ? 745 +636 c48 92 ? 745 +566 c47 93 ? 745 +496 c46 94 ? 745 +426 c45 95 ? 745 +356 c44 96 ? 745 +286 c43 97 ? 745 +216 c42 98 ? 745 +146 c41 99 ? 745 +76 r17dup 100 ? 745 +6 lcd row driver output c40 101 ? 745 ? 64 lcd column driver output c39 102 ? 745 ? 134 c38 103 ? 745 ? 204 c37 104 ? 745 ? 274 c36 105 ? 745 ? 344 c35 106 ? 745 ? 414 c34 107 ? 745 ? 484 c33 108 ? 745 ? 554 c32 109 ? 745 ? 624 c31 110 ? 745 ? 694 c30 111 ? 745 ? 764 c29 112 ? 745 ? 834 c28 113 ? 745 ? 904 c27 114 ? 745 ? 974 c26 115 ? 745 ? 1044 c25 116 ? 745 ? 1114 c24 117 ? 745 ? 1184 c23 118 ? 745 ? 1254 c22 119 ? 745 ? 1324 c21 120 ? 745 ? 1394 table 46. pin location ?continued all x and y coordinates are referenced to the center of the ch ip (dimensions in m). symbol pin x y description
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 75 of 83 nxp semiconductors pcf2119x lcd controllers/drivers c20 121 ? 745 ? 1464 lcd column driver output c19 122 ? 745 ? 1534 c18 123 ? 745 ? 1604 c17 124 ? 745 ? 1674 c16 125 ? 745 ? 1744 c15 126 ? 745 ? 1884 c14 127 ? 745 ? 1954 c13 128 ? 745 ? 2024 c12 129 ? 745 ? 2094 c11 130 ? 745 ? 2164 c10 131 ? 745 ? 2234 c9 132 ? 745 ? 2304 c8 133 ? 745 ? 2374 c7 134 ? 745 ? 2444 c6 135 ? 745 ? 2514 c5 136 ? 745 ? 2584 c4 137 ? 745 ? 2654 c3 138 ? 745 ? 2724 c2 139 ? 745 ? 2794 c1 140 ? 745 ? 2864 r18 141 ? 745 ? 2934 lcd row driver output r9 142 ? 745 ? 3004 r10 143 ? 745 ? 3074 r11 144 ? 745 ? 3144 r12 145 ? 745 ? 3214 r13 146 ? 745 ? 3284 r14 147 ? 745 ? 3354 r15 148 ? 745 ? 3424 r16 149 ? 745 ? 3494 dummy (v ss1 ) 150 ? 745 ? 3704 dummy scl 151 +745 ? 3704 i 2 c-bus serial clock input scl 152 +745 ? 3634 t3 153 +745 ? 3494 test pin 3 por 154 +745 ? 3424 external power-on reset (por) input pd 155 +745 ? 3214 power-down mode select input sda 156 +745 ? 3004 i 2 c-bus serial data input/output sda 157 +745 ? 2934 r/w 158 +745 ? 2584 read/write input rs 159 +745 ? 2374 register select input db0 160 +745 ? 2164 8-bit bidirectional data bus; bit 0 table 46. pin location ?continued all x and y coordinates are referenced to the center of the ch ip (dimensions in m). symbol pin x y description
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 76 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 18. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. db1 161 +745 ? 1954 8-bit bidirectional data bus; bit 1 db2 162 +745 ? 1744 8-bit bidirectional data bus; bit 2 db3/sa0 163 +745 ? 1534 8-bit bidirectional data bus; bit 3 db4 164 +745 ? 1324 8-bit bidirectional data bus; bit 4 db5 165 +745 ? 1114 8-bit bidirectional data bus; bit 5 db6 166 +745 ? 904 8-bit bidirectional data bus; bit 6 db7 167 +745 ? 694 8-bit bidirectional data bus; bit 7 osc 168 +745 ? 484 oscillator or external clock input table 47. alignment mark location all x and y coordinates are referenced to the center of the ch ip (dimensions in m). symbol pin x y am1 - +745 ? 2689 am2 - +745 +2561 am3 - ? 745 +3681 am4 - ? 745 ? 3599 table 46. pin location ?continued all x and y coordinates are referenced to the center of the ch ip (dimensions in m). symbol pin x y description
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 77 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 19. packing information for dimensions see table 48 . tray has pockets on both, front side and back side. fig 50. tray details table 48. tray dimensions dimension description value a pocket pitch x direction 10.89 mm b pocket pitch y direction 4.34 mm c pocket width x direction 7.69 mm d pocket width y direction 1.8 mm e tray width x direction 50.7 mm f tray width y direction 50.7 mm x pockets in x direction 4 y pockets in y direction 10 001aai624 e f b d c a x.1 x y 1.2 1.3 2.2 3.1 1.y 2.1 1.1
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 78 of 83 nxp semiconductors pcf2119x lcd controllers/drivers the orientation of the ic in a pocket is indica ted by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. refer to the bonding pin location diagram for the orientating and pos ition of the type name on the die surface. fig 51. tray alignment 001aaj62 3 marking code
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 79 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 20. abbreviations table 49. abbreviations acronym description cgram character generator ram cgrom character generator rom cmos complementary metal-oxide semiconductor cog chip-on-glass dc direct current ddram display data ram hbm human body model i 2 c inter-integrated circuit ic integrated circuit ito indium tin oxide lcd liquid crystal display lsb least significant bit mm machine model msb most significant bit mux multiplexer pcb printed-circuit board por power-on reset ram random access memory rms root mean square rom read only memory scl serial clock line sda serial data line
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 80 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 21. references [1] an10170 ? design guidelines for cog modules with nxp monochrome lcd drivers [2] an10706 ? handling bare die [3] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [4] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [5] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [6] jesd22-a115 ? electrostatic discharge (esd) se nsitivity testing machine model (mm) [7] jesd78 ? ic latch-up test [8] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [9] nx3-00092 ? nxp store and transport requirements [10] um10204 ? i 2 c-bus specification and user manual 22. revision history table 50. revision history document id release date data sheet status change notice supersedes pcf2119x v.9 20110414 product data sheet - pcf2119x v.8 modifications: ? corrected product type naming pcf2119x v.8 20110404 product data sheet - pcf2119x v.7 pcf2119x v.7 20101115 product data sheet - pcf2119x v.6 pcf2119x v.6 20100908 product data sheet - pcf2119x_5 pcf2119x_5 20090813 product data sheet - pcf2119x_4 pcf2119x_4 20030130 product specification - pcf2119x_3 pcf2119x_3 20020116 product specification - pcf2119x_2 pcf2119x_2 19990302 product specification - pcf2119x_1 pcf2119x_1 19971121 objective specification - -
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 81 of 83 nxp semiconductors pcf2119x lcd controllers/drivers 23. legal information 23.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 23.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 23.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
pcf2119x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 14 april 2011 82 of 83 nxp semiconductors pcf2119x lcd controllers/drivers non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. bare die ? all die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 23.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 24. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pcf2119x lcd controllers/drivers ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 14 april 2011 document identifier: pcf2119x please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 25. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . . 8 8.1 oscillator and timing generator. . . . . . . . . . . . . 8 8.1.1 timing generator. . . . . . . . . . . . . . . . . . . . . . . . 8 8.1.2 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1.3 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2 reset function and power-on reset (por) . . . 8 8.3 power-down mode . . . . . . . . . . . . . . . . . . . . . . 9 8.4 lcd supply voltage generator . . . . . . . . . . . . 10 8.4.1 programming ranges . . . . . . . . . . . . . . . . . . . 10 8.5 lcd bias voltage generator . . . . . . . . . . . . . . 11 8.5.1 electro-optical performance . . . . . . . . . . . . . . 12 8.6 lcd row and column drivers . . . . . . . . . . . . . 13 9 display data ram and rom . . . . . . . . . . . . . . 17 9.1 ddram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.2 cgrom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.3 cgram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.4 cursor control circuit. . . . . . . . . . . . . . . . . . . . 26 10 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.1 data register . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2 instruction register . . . . . . . . . . . . . . . . . . . . . 28 10.2.1 basic instructions (bit h = 0 or 1) . . . . . . . . . . 30 10.2.1.1 function_set . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.2.1.2 bf_ac instructions . . . . . . . . . . . . . . . . . . . . . 30 10.2.1.3 read_data . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2.1.4 write_data . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2.2 standard instructions (bit h = 0) . . . . . . . . . . . 32 10.2.2.1 clear_display . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2.2.2 return_home . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2.2.3 entry_mode_set . . . . . . . . . . . . . . . . . . . . . . . 33 10.2.2.4 display_ctl instructions . . . . . . . . . . . . . . . . . . 33 10.2.2.5 curs_disp_shift . . . . . . . . . . . . . . . . . . . . . . . . 34 10.2.2.6 set_cgram . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2.2.7 set_ddram . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2.3 extended instructions (bit h = 1) . . . . . . . . . . 36 10.2.3.1 screen_conf . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2.3.2 disp_conf . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2.3.3 icon_ctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.2.3.4 temp_ctl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2.3.5 hv_gen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2.3.6 vlcd_set. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11 basic architecture . . . . . . . . . . . . . . . . . . . . . . 42 11.1 parallel interface . . . . . . . . . . . . . . . . . . . . . . 42 11.2 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . 44 11.2.1 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 45 11.2.2 i 2 c-bus definitions . . . . . . . . . . . . . . . . . . . . . 45 12 internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 48 13 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 49 14 static characteristics . . . . . . . . . . . . . . . . . . . 50 15 dynamic characteristics. . . . . . . . . . . . . . . . . 52 16 application information . . . . . . . . . . . . . . . . . 55 16.1 general application informa tion . . . . . . . . . . . 55 16.2 power supply connections for internal v lcd generation . . . . . . . . . . . . . . . . . . . . . . . 55 16.3 power supply connections for external v lcd generation . . . . . . . . . . . . . . . . . . . . . . . 56 16.4 information about v lcd connections . . . . . . . 56 16.5 reducing current consumption . . . . . . . . . . . 56 16.6 charge pump characteristics . . . . . . . . . . . . . 57 16.7 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.8 connections with lcd modules. . . . . . . . . . . 60 16.9 4-bit operation, 1-line display using external reset . . . . . . . . . . . . . . . . . . . . . . . . . 61 16.10 8-bit operation, 1-line display using external reset . . . . . . . . . . . . . . . . . . . . . . . . . 61 16.11 8-bit operation, 2-line display . . . . . . . . . . . . . 64 16.12 i 2 c-bus operation, 1-line display . . . . . . . . . . 65 16.13 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 67 16.14 user defined characters and symbols . . . . . . 69 17 bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 71 18 handling information . . . . . . . . . . . . . . . . . . . 76 19 packing information . . . . . . . . . . . . . . . . . . . . 77 20 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 79 21 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 22 revision history . . . . . . . . . . . . . . . . . . . . . . . 80 23 legal information . . . . . . . . . . . . . . . . . . . . . . 81 23.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 81 23.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 23.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 81 23.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 82 24 contact information . . . . . . . . . . . . . . . . . . . . 82 25 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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